Electronic Echo

General description, timing diagram, and circuit diagram

The concept of this electronic echo is
  1. to convert the analog microphone signal into a sequence of digital samples,
  2. to store the samples into a cyclically organised memory,
  3. to read them out after one cycle (the delay corresponds to the cycle length and the sampling rate),
  4. to convert the samples back to an analog signal,
  5. to amplify the signal and feed it to a speaker.
Because we were short in time, we had to buy all the stuff for accomplishing the above tasks at the Conrad-Electronics shop in Dresden. Therefore, we used the following main components:

The circuit diagram is split into an analog part and a digital part. Click on the following thumbnails to get the corresponding circuit diagrams in DIN A4 postscript format.
Thumbnail echo-digital Thumbnail echo-analog
Digital part. Analog part.

Note, that this is my first use of Eagle-light. So, please excuse graphical imperfections in the circuit diagrams.

The next figure shows the timing diagram.

For the description of the timing diagram, we assume that the sampling frequency of the ADC is 10kHz. As mentioned above, this frequency can be up-scaled as much as the decreasing conversation quality of the DAC admits.

With the help of two D-Flipflops two 20kHz clock-signals Clk and ClkD are derived from some 40kHz-square signal. Thereby, ClkD is a 90°-delayed version of Clk.

The counter is driven by the Clk signal. The bits CT1 to CT15 of the counter are used for the address bus of the memory. That means that the memory address is incremented with a frequency of 10kHz -- half the frequency of Clk.

  1. In the phase Ct0=low the memory at the current address is read and the corresponding value is feed to the output buffer (low-high-transition of the signal DFF,Clk ). At the same time the ADC is initialized (high-low transition of /ADC,WR) and the conversion cycle of the ADC is started (low-high transition of /ADC,WR).
  2. In the phase Ct0=high the ADC is read (low phase of /ADC,RD) and with the low-high transition of the memory chip enable signal (/M,CE) the output of the ADC is written into the RAM at the current address.

    In my first design of the timing diagram I planned some delay between the low-high transition of /M,CE and the low-high transition of /ADC,RD. That complicated the circuit diagram. Frank Dachselt checked the timing diagram for me. He suggested to use the same low-high transition for /ADC,RD and /M,CE. That works since the memory is very fast and from /M,CE to /ADC,RD there is some logic that introduces some gate delay. That simplified the design quite a bit. Thank you, Frank!

  3. At the next high-low transition of Ct0 the address is incremented and the whole game starts again.

Active Butherworth filters of third order are used as anti-aliasing filter and as reconstruction filter (steep filters are needed because of the relatively low oversampling).

The active anti-aliasing filter also works as the microphone pre-amplifier. The pre-amplification level can be adjusted by the potentiometer R3.

Thomas Falk helped me with testing of the circuit in a lab at the electronical department of TU-Dresden. Since I left my magnification glasses at home I could not see the solder pads. So, he also made some necessary changes for me. Thank you, Thomas!

A picture

Click on the thumbnail to enlarge the picture.